The present invention relates to semiconductor integrated circuits, and more particularly, to a system circuit incorporating memories and logic circuits.
The demand for combined memory/logic type system LSIs has increased in recent years. In such a system LSI, a plurality of memories are incorporated in a single device to meet the demands for decreasing power consumption and providing more functions. There is also a demand for decreasing the time required for testing the system LSI.
FIG. 1 shows an example of a prior art system LSI. The system LSI 1 includes two memory macros 2, 3, each having a memory capacity of 2MB, a memory macro 4 having a memory capacity of 8MB, and two logic circuits 5, 6. All of the circuits 2-6 are arranged at predetermined positions on a chip. Referring to FIG. 2, as known in the prior art, each of the memory macros 2-4 includes a memory cell array 10, a row decoder 11, a column decoder 12, an input/output circuit 13, an input buffer circuit 14, a mixer 15, and a power supply circuit 16. The memory macros 2, 3 differ from the memory macro 4 only in memory capacity and circuit scale, which is related to the memory capacity.
The power supply circuit 16 includes a pull-down circuit 20, which is shown in FIG. 3. The pull-down circuit 20 is provided with a trimming circuit 21, a reference voltage generating circuit 22, a control circuit 23, and a power supply driver circuit 24. The control circuit 23 receives an enable signal EN. The control circuit 23 shifts the power supply driver circuit 24 between an activated state and a deactivated state in accordance with the enable signal EN. The reference voltage generating circuit 22 sends a reference voltage V.sub.r to the power supply driver circuit 24. The power supply driver circuit 24 decreases the voltage of an external power supply based on the reference voltage V.sub.r and generates an internal power supply V.sub.in. The internal power supply V.sub.in is sent to, for example, the memory cell array 10 as an operational power supply.
As shown in FIG. 4, the trimming circuit 21 includes two fuse circuits 31, 32 and four AND circuits 33-36. The fuse circuit 31 has a first NMOS transistor T.sub.r1, a fuse f01, and two inverters 31a, 31b. The source of the first NMOS transistor T.sub.r1 is connected to a low potential power supply V.sub.SS. The drain of the first NMOS transistor T.sub.r1 is connected to the high potential power supply V.sub.CC via the fuse f01 and to its gate via the inverter 31a. The drain of the first NMOS transistor T.sub.r1 outputs a detection signal n01z. The detection signal n01z is inverted by the inverter 31b and output as a detection signal n01x.
The fuse circuit 32 has a second NMOS transistor T.sub.r2, a fuse f02, and two inverters 32a, 32b. The structure of the fuse circuit 32 is identical to that of the fuse circuit 31. The drain of the second NMOS transistor T.sub.r2 outputs a detection signal n02z. The detection signal n02x is also output from the drain of the second NMOS transistor Tr.sub.2 via the inverter 32b.
The detection signals n01x, n02z are received by the first AND circuit 33. An output voltage V1 is output from the output terminal of the first AND circuit 33 in accordance with the signals n01x, n02z. The detection signals n01z, n02z are received by the second AND circuit 34. An output voltage V2 is output from the output terminal of the second AND circuit 34 in accordance with the signals n01z, n02z. The detection signals n01z, n02x are received by the third AND circuit 35. An output voltage V3 is output from the output terminal of the third AND circuit 35 in accordance with the signals n01z, n02x. The detection signals n01x, n02x are received by the fourth AND circuit 36. An output voltage V4 is output from the output terminal of the fourth AND circuit 36 in accordance with the signals n01x, n02x. The first to third AND circuits 33-35 are each connected to the reference voltage generating circuit 22.
As shown in FIG. 4, the reference voltage generating circuit 22 includes a resistor R and seven NMOS transistors T.sub.r3 -T.sub.r9. The resistor R and the four NMOS transistors T.sub.r3 -T.sub.r6 are connected in series between the high potential power supply V.sub.CC and the low potential power supply V.sub.SS. The gate and drain of each NMOS transistor T.sub.r3 -T.sub.r6 are connected to each other. That is, each of the NMOS transistors T.sub.r3 -T.sub.r6 acts as a diode.
The source of the third NMOS transistor T.sub.r3 is connected to the low potential power supply V.sub.SS via the seventh NMOS transistor T.sub.r7. The drain of the third NMOS transistor T.sub.r3 is an output node. The reference voltage V.sub.r is sent from the output node to a measuring pad P, which is arranged on the power supply driver circuit 24. The gate of the seventh NMOS transistor T.sub.r7 receives the output voltage V1. The source of the fourth NMOS transistor T.sub.r4 is connected to the low potential power supply V.sub.SS via the eighth NMOS transistor T.sub.r8. The gate of the eighth NMOS transistor T.sub.r8 receives the output voltage V2. The source of the fifth NMOS transistor T.sub.r5 is connected to the low potential power supply V.sub.SS via the ninth NMOS transistor T.sub.r9. The gate of the ninth NMOS transistor T.sub.r9 receives the output voltage V3.
As shown in FIG. 5, in the trimming circuit 21 and the reference voltage generating circuit 22, only the output voltage V2 goes high when both fuses f01, f02 do not undergo trimming (as indicated by the circles). In this case, the eighth NMOS transistor T.sub.r8 is activated. Accordingly, the reference voltage V.sub.r has a level obtained by distributing the potential difference between the high potential power supply V.sub.CC and the low potential power supply V.sub.SS to the resistor R and the ON resistance of the two NMOS transistors T.sub.r3, T.sub.r4.
If trimming is performed on only the fuse f01 (as marked by the "X"), only the output voltage V1 goes high. In this case, the seventh NMOS transistor T.sub.r7 is activated. Accordingly, the reference voltage V.sub.r has a level obtained by distributing the potential difference between the high potential power supply V.sub.CC and the low potential power supply V.sub.SS to the resistor R and the ON resistance of the third NMOS transistor T.sub.r3.
If trimming is performed on only the fuse f02, only the output voltage V3 goes high. In this case, the ninth NMOS transistor T.sub.r9 is activated. Accordingly, the reference voltage V.sub.r has a level obtained by distributing the potential difference between the high potential power supply V.sub.CC and the low potential power supply V.sub.SS to the resistor R and the ON resistance of the three NMOS transistors T.sub.r3 -T.sub.r5.
If trimming is performed on both of the fuses f01, f02, only the output voltage V4 goes high, while output voltages V1-V3 all go low. Accordingly, the NMOS transistors T.sub.r7 -T.sub.r9 remain deactivated. As a result, the reference voltage V.sub.r has a level obtained by distributing the potential difference between the high potential power supply V.sub.CC and the low potential power supply V.sub.SS to the resistor R and the ON resistance of the four NMOS transistors T.sub.r3 -T.sub.r6.
When testing the system LSI 1 before shipment out of the factory, the reference voltage V.sub.r output from the measuring output pad P is measured by a measuring apparatus to determine whether or not the reference voltage V.sub.r is within a predetermined range. If the measured reference voltage V.sub.r is not in the predetermined range, trimming is carried using the fuses f01, f02 in accordance with the amount offset from the predetermined range. The reference voltage generating circuit 22 generates the reference voltage V.sub.r in accordance with the level based on the combination of the fuses f01, f02 that undergo or do not undergo trimming, or in accordance with the predetermined voltage value. Such trimming is conducted on each of the memory macros 2-4.
The system LSI 1 is designed by a layout apparatus (CAD apparatus). As shown in FIG. 1, library data such as logic circuits or memory macros including the memory macros 2-4 are stored in a library Lb. Various types of information such as layout data and net information are also included in the library data.
Each memory macro is formed so that it operates as a single unit. Accordingly, the CAD apparatus selects the memory macro having the desired memory capacity from the library Lb and arranges the selected memory macro on a chip to design the system LSI with the memory function of the selected memory macro.
As a result, the number of trimming circuits 21 in the system LSI 1 is equal to the number of memory macros arranged in the system LSI 1 (three trimming circuits 21 for the above three memory macros 2-4). When the system LSI 1 is tested prior to shipment out of the factory, the reference voltage V.sub.r is measured and trimming is conducted on each of the memory macros. Thus, a long time is required for the testing. The long testing time increases the cost of the system LSI.
Furthermore, a measuring pad P must be provided for the pull-down circuit 20 of each memory macro 2-4 in the chip on which the system LSI 1 is formed. The plurality of measuring pads P interferes with high integration of the system LSI 1.
This problem is not limited to only the pull-down voltage circuit 20. For example, the power supply circuit 16 includes a substrate potential generating circuit (not shown) which generates a substrate potential. The substrate potential generating circuit includes a power supply driver circuit, a detection circuit, and a trimming circuit similar to that of FIG. 4. The detection circuit detects the substrate potential and sends the detection signal to the power supply driver circuit. The power driver circuit generates the substrate potential based on the detection signal. A measuring pad is arranged on the chip to measure the substrate potential. During testing, the substrate potential at the measuring pad is measured. If the measured value is not included in the predetermined range, trimming is conducted on the fuse in the trimming circuit so that the measured value enters the predetermined range. Accordingly, the same problems as described above occurs, making the chip more costly.